A 25 MHz-BW 81 dB-DR TDC-Based CTDSM With Background Analog-Integration-Based ISI Error Calibration Achieving >8 dB Even-Order Harmonic Suppression

This paper presents a 4th-order continuous-time $\Delta \Sigma $ modulator (CTDSM) employing a 6-bit time-domain quantizer. The implemented quantizer employs a time-to-digital converter (TDC)-based architecture which strikes a good balance among speed, resolution and power efficiency. A novel background calibration technique is proposed to mitigate dynamic inter-symbol interference (ISI) errors in multi-bit digital-to-analog converters (DACs) while introducing negligible additional excess loop delay (ELD), power consumption and circuit complexity. The prototype in a 40-nm CMOS is sampled at 630 MHz, achieving an SNDR/SNR/SFDR/DR of 75 dB / 77.9 dB / 86.6 dBc / 81 dB over a signal bandwidth of 25 MHz. The proposed background ISI error calibration scheme suppresses 2nd- and 4th-order harmonics by 8.5 dB and 3.5 dB, respectively. The total power consumption is 21.23 mW, achieving a Schreier Figure of Merit (FoMs) of 171.7 dB.