CHEF: CHaracterizing Elusive Logic Circuit Failures

Logic circuit diagnosis is an essential tool for improving manufacturing yield. However, there is a significant disparity between the behavior predicted by conventional fault models and the actual behavior observed in failing circuits. This undermines the performance of diagnosis methodologies that rely on conventional fault models to characterize defect behavior. Recently, a parameterizable test metric called PEPR has demonstrated the ability to precisely bound defect behavior, even when it deviates from conventional fault model assumptions. This paper describes a novel diagnosis methodology that uses the PEPR metric to determine (i) the physical location of a defect and (ii) the precise changes to the logic functionality of the affected circuit in the form of a custom fault model. The methodology, called CHEF, is applied to over 700 fail logs from a 22nm industrial test chip. Results demonstrate CHEF precisely characterizes defects that conventional diagnosis cannot, specifically when failure behavior does not align with a conventional fault model. Furthermore, CHEF achieves a significant increase in diagnostic resolution compared to conventional diagnosis, more than doubling the number of failures with a physical resolution better than 1µm². Finally, diagnostic patterns generated by CHEF demonstrate the capability to further refine defect characterization.