Test, Debug, and Repair for Chiplet-Based Designs

Chiplet-based systems introduce new challenges in test, debug, and repair. The complexity and number of interconnects increase the likelihood of defects, necessitating repair strategies to prevent discarding expensive systems due to a few faulty interconnects. To address these challenges, the IEEE P3405 "Standard for Chiplet Interconnect Test and Repair" is under development. This standard, originating from IEEE 1838-2019, aims to be universally applicable beyond IEEE 1838-based multi-die designs. The goal of P3405 is to standardize the test, repair, and potentially debug and diagnosis of interconnect hardware between chiplets, particularly for heterogeneous, multi-vendor integration flows. This session will present talks covering various aspects of these challenges, including the need for a language to communicate the structural and functional details of interconnects and repair options. The second presentation will focus on challenges and solutions related to clock interconnect testing and the impact of high-speed clocking. Finally, the last talk will address the testing of analog circuitry in chiplets and its application to enable high-speed communication.