GLLaMoR: Graph-based Logic Locking by Large Language Models for Enhanced Robustness

Logic locking protects integrated circuits (ICs) from design piracy. The idea is to insert key-controlled components, a.k.a. key-gates, to lock the IC’s functionality, where the correct key is the designer’s secret. The robustness of logic locking can be enhanced by carefully identifying best locations to insert key-gates, e.g., by analyzing the IC’s topology and lock parts with high impact on functional behaviour. Traditionally, the challenge of identifying critical locations relies on computationally-intensive graph traversal and design methods like fault analysis. The rise of large language models (LLMs), which have recently demonstrated proficiency also on complex graph data, presents an interesting opportunity to revisit this challenge. Here, we present GLLaMoR, a first-of-its-kind framework using LLMs on graph-based IC representations to identify critical locking locations. Through LLM performance evaluation and end-to-end case studies, we demonstrate that GLLaMoR paves the way for more effective and scalable logic locking.