Fault Modeling and Testing of ReRAM-based CAM Array

Measuring similarity between binary patterns is a key kernel in various data-intensive applications such as search engines and artificial intelligence (AI). However, due to the memory wall problem caused by frequent data transfers between processor cores and memory subsystems, executing these operations leads to high energy consumption and increased latency. One approach to mitigating this problem is to utilize Computing-in-Memory (CiM) architectures for the realization of Content-Addressable Memory (CAM) in such applications. Integrating Non-Volatile Memory (NVM) technologies can improve performance and energy efficiency. Redox-based Resistive Access Memory (ReRAM) is a promising candidate for implementation within NVM-based Content-Addressable Memory (CAM) due to its non-volatile nature, low power consumption, and highly distinct resistive levels. However, integrating NVM with conventional CMOS introduces unique fabrication challenges and failure mechanisms that are not seen in CMOS processes alone. Furthermore, the analog nature of CiM increases sensitivity to non-idealities in both ReRAM and CMOS, resulting in new fault behaviors that affect the quality of ReRAM-based CAM (ReCAM) blocks. Therefore, to ensure the high quality of the ReCAM functionality, this paper develops a March-like test algorithm tailored for the ReCAM array. The proposed March-like test algorithm is extendable and can achieve 100% fault coverage.