Offset Field Extraction With Multi-Bit Magnetic Tunnel Junction Structures

As magnetic tunnel junctions (MTJs) are downscaled and their spin-transfer torque (STT) efficiency improves, measurement effects that complicate accurate device-level characterization become more severe. In this study, we investigate how the constant read current that flows through the MTJ during magnetoresistance hysteresis loop characterization influences the extracted switching fields. We show that in industry-grade single-bit devices, even slight variations in read current magnitude and polarity can significantly alter the switching fields in a nonsymmetric way, thereby shifting the offset field away from its zero-bias value. To minimize this effect, we propose the use of a multi-bit structure composed of a chain of MTJs that are serially connected in head-to-head and tail-to-tail configuration and can be implemented in the scribe line of product wafers. We observe that the bias effect averages out across the structure’s subpopulations and provides a substantially larger sample size per measurement when compared to single-bit devices. We show that this makes the multi-bit structures suitable for identifying process-related inhomogeneities across the wafer. Furthermore, we show that the temperature-dependent offset field extracted from multi-bit structures can be used to predict array-level energy barrier (EB) balance behavior at solder reflow temperatures. Our findings underscore the advantages of multi-bit structures for faster process optimization and device-level testing in a manufacturing setting.