Interplay of Short-Channel and Narrow-Width Effects in FDSOI Transistors at Cryogenic Temperatures

The fully depleted silicon-on-insulator (FDSOI) technology has been a preferred choice for cryo-CMOS IC designers, but the combined effects of scaling both channel length and width, along with temperature variations, have not been extensively explored in the context of super low threshold voltage (SLVT) device technology. The key device figures of merit (FOMs), including threshold voltage ( ${V}_{\text {th}}$ ), drain-induced barrier lowering (DIBL), subthreshold swing (SS), transconductance ( ${g}_{m}$ ), andon-resistance ( ${R}_{\text {ON}}$ ), exhibit varying behaviors under changes in temperature and device scaling. Specifically, ${V}_{\text {th}}$ , DIBL, and SS degrade in narrow-width devices at lower temperatures, while ${I}_{\text {ON}}$ , ${g}_{m}$ , and ${R}_{\text {ON}}$ improve. For short-channel devices, the FOMs behave similar to their room-temperature counterparts, but with a temperature-dependent offset at cryogenic temperatures. The underlying temperature-dependent effects at cryogenic temperatures are further analyzed using TCAD simulations at 8 K and room temperature (RT).