Tutorial: DPLL Based Clock and Data Recovery

The purpose of this tutorial is to introduce attendees to Digital Phase-Locked Loop (DPLL) based Clock-and-Data Recovery (CDR). The talk will start with an overview of different types of CDRs to frame where DPLL-based CDRs fit into the overall landscape. Next, the basic theory behind DPLL-based CDRs will be presented with an eye towards practical application. Following this, the performance of DPLL-based CDRs in the face of various practical impairments such as ISI, random jitter, deterministic jitter, slicer offset, etc will be explored. This part of the talk will also tie into jitter budgets and electrical tables found in standards. Finally, the talk will conclude with an example to show how all the concepts come together into a design.