Tutorial: Layout - The Other Half of Nanometer CMOS Analog Design

The layout of analog blocks has for a long time been a critical aspect to achieving the theoretical performance of a circuit. Perhaps more importantly, when the layout fails to match the design, the project can fail in schedule, cost, or performance. In nanometer CMOS there are many layout-induced effects that alter the transistor characteristics, and this means that matching the layout to the design is becoming more difficult and critical. This tutorial provides an overview of those effects, and provides some strategies and approaches to combat them. Even if you don't do the layout yourself, every designer should be able to guide the process through to success.