Delay and Power Optimization in 8-Bit ALU Using Reversible Logic

Arithmetic Logic Units (ALUs) play a crucial role in digital processing, where optimizing power consumption and delay is essential for improved performance. The traditional low power 8-bit ALU on Reversible logic for nano processors [DRA-8] used the Dual Key Gate Pair (DKGP) gate. The proposed 8-bit ALU implements Haghparast and Navi Gate (HNG) and Control Output Gate (COG), leading to significant differences in architecture and performance. This ALU is evaluated based on power dissipation and delay, demonstrating a significant reduction in both compared to the DRA-8 design. The comparative analysis highlights trade-offs in circuit complexity, gate count, and garbage outputs, showcasing the efficiency of the optimized approach. The results confirm that the proposed Delay and Power optimization in 8-bit ALU using reversible logic (DPA-8) achieved superior power-delay performance, making it highly suitable for low-power, high-speed computing applications, particularly in nano processors and emerging reversible computing technologies.