Comparative Study of Transistor Logic Families in Half Adder Circuit Design

This work analyses the half-adder circuit in different transistor logic families such as CMOS, Psuedo nMOS, Transmission Gate, Pass Transistor, Dynamic CMOS and Domino CMOS logics for area in terms of transistors count, power consumption and time delays. The simulation results show that the listed transistor families are the most efficient and highlighting on advantages and disadvantages of each transistor family. These analyses are done by using Tanner EDA environment. For lower area and power consumption Pass Transistor logic can be implemented, occupying 40% of the workspace in comparison with Complementary MOS design style. For higher speeds applications Domino or Dynamic CMOS Logics are suitable and consume less power.