VLSI Implementation of Pipelined PE Systolic Array-Based 3x3 Matrix Multiplication for Deep Neural Network Accelerator

The demand for efficient, low-power, and high-speed deep neural network (DNN) accelerators has driven the need for specialized hardware architectures. This work presents the VLSI implementation of a DNN accelerator, building upon a prior project that utilized the systolic array architecture. We eliminate the conventional for-loop multiplication approach, leveraging the systolic array's data parallelism and pipelining to reduce clock cycle delays. The ReLU activation function is integrated into the systolic array to enable nonlinear transformations. Experimental results, obtained using 28nm technology using Synopsys Design Compiler, show that the systolic array with ReLU achieves a 19.9% power reduction and maintains a delay of 0.19 ps, with a marginal 0.69% area increase compared to the systolic array without ReLU. Pipelining further reduces clock cycle delays, enhancing real-time processing. This work demonstrates the potential of combining RNS, systolic arrays, and pipelining to design scalable, high-performance DNN accelerators for advanced tasks.