An Overview: Differential Logic Full Adder Design, Merits and Demerits

This paper discusses the designing of full adder circuits using CMOS differential logic family. Due to the increase in the transistor count in VLSI circuit, it is necessary to miniaturize the device size and power dissipated. This paper also provides a clear view of schematic design, switching logic and power consumed by the different CMOS logics in comparison with differential logic circuit in MentorGraphics environment.