Dual-Gate 2T0C Gain Cell for Multi-Bit Input Vector-Matrix Multiplication in-Memory Computing

In this work, one novel dual-gate 2T0C is proposed for multi-bit input vector-matrix multiplication (VMM) in in-memory computing (IMC). Unlike the existing pulse-width modulation (PWM) method for implementing multi-bit input, the proposed approach utilizes pure voltage control to adjust the gate voltage of the dual-gate 2T0C, thus enabling high-speed computing. Validity of this multi-bit input scheme is confirmed by simulation with high linearity (~99.4%) of current versus gate bias of read transistor. In addition, the dual-gate 2T0C can achieve a high linearity (~97.9%) of current dependence on weight by using current programming. It indicates that the dual-gate 2T0C is promising for IMC.