Enhancing Alliance VLSI Toolchain by Mixed Gate-level Logic Synthesis

Alliance is an open-source CAD tool suite for very large scale integration (VLSI) design, offering a comprehensive set of features including VHDL compiler, simulator, logic synthesis tools, and automatic place and route (P&R) capabilities. However, the logic synthesis tool within Alliance faces limitations when handling large-scale circuits. To address this issue, we propose an approach that extends Alliance’s ability to handle large circuits and improve the results after technology mapping. Experimental results on the EPFL benchmark suite demonstrate an average improvement of 20% in delay and a 15% reduction in area compared to the original performance of Alliance.