A Multi-Step ADC With Lightweight Input Buffer Distortion, Sub-Stage Coarse-Fine Gain, and Sampling Skew Background Calibrations

This paper presents a lightweight background calibration for the distortion of the analog-to-digital converter (ADC)’s input buffer. The buffer’s nonlinearity is calibrated on-chip by the Harmonic-Compensated Diode Load (HC-DL), whose bias voltage is determined by the calibration algorithm facilitated by dither injection at the input of the buffer. A two-step ADC is exploited to demonstrate the calibration, where the coarse-fine ADC gain mismatch and sampling skew at the $1^{\mathbf {st}}$ step are calibrated by monitoring the occupation of the correction range (OCR) at the $2^{\mathbf {nd}}$ step. Verified in a 12b 1 GS/s pipe-SAR ADC in 28 nm CMOS, the SNDR and SFDR at Nyquist input are 60.96 dB/76.8 dB, respectively and the SFDR keeps >75 dB over PVT.