Iteration and SDA-Driven LDPC Decoding Latency Reduction for 3-D TLC NAND Flash Memory

To enhance the reliability of 3-D TLC NAND flash memory, low-density parity-check (LDPC) codes have become widely adopted. However, as the number of read, program or erasures increases, the raw bit error rate (RBER) of read data in flash memory chips also rises, leading to the challenge of increased LDPC decoding latency. To address this, an idea of utilizing the decoding correct probability of LDPC to reduce latency is proposed. First, by analyzing the encoding method of TLC NAND flash memory, a single direction characterization error model based on the correlation between individual pages is constructed. Next, through experimental validation, the feasibility of using the number of iterations as an indicator of decoding correct probability is demonstrated, leading to the proposal of a low-overhead and high-performance Iterative Alternative Correct Probability Optimization (IACPO) scheme. Leveraging the fact that LDPC decoding exhibits a high success probability within a specific range of read data, the existence of successful decoding area (SDA) is confirmed through a large number of real experiments, and the distribution characteristics of SDA in TLC NAND flash memory are analyzed. Finally, the Utilizing LDPC Decoding Correct-Probability Optimization (ULDCO) scheme to further optimize latency is proposed. This scheme uses SDA to improve the probability of correct data reading, particularly in the middle and later stages of flash memory life, in combination with the IACPO scheme. Experimental results show that the proposed IACPO and ULDCO schemes are not only generally applicable but also achieve significantly iterative latency reduction by 73.43% and 81.51%, respectively, compared to traditional schemes, with negligible storage and computation overhead. These results clearly demonstrate the superior performance of the proposed schemes in reducing iteration latency.