Enhanced emitter-coupled logic (EECL)

Design enhancements to emitter coupled logic are proposed. In the enhanced emitter-coupled logic (EECL) circuits (a) no reference voltage (V/sub bb/) is required, (b) complex logic functions containing a mix of complemented and uncomplemented input signals may be realized in a single gate stage, (c) the diode clamps commonly used when collector-dotting ECL circuits are not required, and (d) signal and supply voltage compatibility with standard ECL is maintained. Also operation is possible with low supply voltages. Elimination of the requirement for a reference voltage (V/sub bb/) to be routed to every gate can result in simpler chip power busing and reduced chip area. The delay through a two-input exclusive-OR (averaged over all combinations of input switching) has been measured on a Schottky-diode EECL, a resistor-divider EECL, and a two-level series ECL circuit. The Schottky-diode EECL circuit is about 0.5 ns faster than resistor-divider EECL, and 1 ns faster than two-level series ECL. Combinatorial and sequential functions, such as selectors, decoders, full adders, D-latches and scan latches, have been designed in EECL. Functions designed in EECL offer reduced gate and/or component count, higher speed, and lower power consumption than standard ECL.<>