An Effective Method to Compensate for Testing Induced SBFET Degradation by Charging Deep-Level Interface Trap

In this paper, the threshold voltage ( $V_{\mathrm {th}}$ ) of Schottky barrier field effect transistors (SBFETs) based on ultra-thin silicon on insulator (SOI) wafer shift induced by electrical test is analyzed. Repeated testing gives rise to a positive shift of the $V_{\mathrm {th}}$ , which is similar to the constant voltage stress effect found in two-dimensional materials. The series resistance of Source and Drain ( $R_{\mathrm {sd}}$ ), mobility ( $\mu $ ), and trapped charge are studied. The positive $\Delta V_{\mathrm {th}}$ is independent of the $R_{\mathrm {sd}}$ and $\mu $ , but related to the deep-level acceptor interface trap, which is charged during the test. The main reason for trap charging is that the Source and Drain contact prepared by metal deposition cannot provide electrons for trap capturing before testing. In order to compensate for the $\Delta V_{\mathrm {th}}$ induced by the test, a deep-level trap charging method is proposed. The necessity of this new test method is verified by irradiation experiments.