USB Host IP Implementation in Shakti Processor

This paper presents the integration of a USB host IP module into the Shakti Processor architecture to enable seamless communication with USB peripherals. The design aims to enhance the processor’s versatility and compatibility with a wide range of USB devices. The USB 2.0 system architecture includes key components such as the USB 2.0 Serial Interface Engine (SIE) for managing communication, the USB 2.0 ULPI PHY for signal conversion, and various controllers for data transfer and power management. FIFO interfaces are employed to buffer data, while AXI interfaces facilitate efficient memory access and register management. The proposed architecture supports high-speed data transfer and ensures robust USB functionality, expanding the Shakti Processor’s capabilities in USB integration.