An Optimized FPGA Based Canny Edge Detection System Using High-Level Synthesis

The Canny edge detection algorithm is one of the most reliable and popular edge detection algorithms that uses a multi-stage algorithm to detect a wide range of edges in images. This paper presents an optimized hardware accelerated implementation of the Canny edge detection algorithm on Zynq 7000 AP SoC. We offer two optimization algorithms embedded in our Canny edge detection process. Firstly, our implementation uses an optimized approximation algorithm (OAA) to calculate the gradient direction, whilst not compromising the quality of the edge detection process. Our OAA uses significantly less hardware resources compared to alternative CORDIC algorithms used by most of the other implementations. Secondly, we propose a hardware-based optimized hysteresis edge tracking (OHET) algorithm to ensure our IP core produces the final image with consistent and crisp edges. The implementation offered by this paper not only accelerates the edge detection process, but also optimizes the implementation process using high level synthesis (HLS). The proposed implementation also leverages a rich set of directives offered by Vivado HLS tool, further optimizing the design and providing greater control over the hardware implementation. We accelerate the software algorithm by incorporating parallelism into several design components such as noise removal through Gaussian, edge detection using the Sobel operators, non-maximum suppression, edge thinning, and finally hysteresis edge tracking. Our hardware acceleration approach on Xilinx Zynq 7000 AP SoC FPGA running at 100 MHz, achieves a speed up of 2.6-630x in execution time depending on the image size compared to software-based implementation on single CPU Cortex-A9 running at 667 MHz. This offers a significant speed up in performance and computational tasks over its software counterpart. Specifically, our implementation processes a 512x512 image in 11.5 ms at 100 MHz.