Hybrid-Type Power-Over-Data-Line Filters for Mode Conversion Noise Reduction

This paper proposes a new approach for mode conversion noise reduction under asymmetric bias conditions in Gbps-class power-over-data-line (PoDL) communications. The proposed approach provides a hybrid circuit configuration of regular inductor components and differential mode inductors as a PoDL filter circuit configuration that is unlikely to experience imbalance of $\mathrm{P} / \mathrm{N}$ electrical characteristics caused by asymmetric bias voltages of $\mathbf{P} / \mathbf{N}$ components. By applying this configuration, mode conversion noise can be suppressed over a wide frequency range from 1 MHz to several GHz under asymmetric bias conditions.