Die Area Reduction by Decongesting Top Channels Using Novel Feedthrough Insertion Methodology in Hierarchical SoC Designs

Die size reduction has been one of the foremost objectives in systems-on-chip (SoC) designs. While previous approaches attempt it by reducing congestion of chip as a whole, there is little attempt to specifically decongest top channel. In channel based hierarchical non-IO limited SoC designs, feedthrough insertion can be an important step in floorplan stage to improve the routing resource utilization, decongest top channels and hence the die area saving. Usual feedthrough insertion approaches are implemented manually or handled in flatten design, however it is challenging to deal with the large number connections on the top, high dependency with RTL, porting new feedthrough ports at subchip level, and logical equivalence coherency checkout. We present a scheme to conquer these issues by using a novel feedthrough insertion methodology.