Design of CMOS D Flip-Flop with Different Supply Voltages

Effective design of arithmetic circuits is important for contemporary digital systems, such as processors and signal processors. With the growth in transistor density, it has become possible to integrate several arithmetic units on a single chip. Many-Valued Logic (MVL) offers a viable method for minimizing chip surface area and lowering computational complexity. This paper deals with the design and analysis of ternary circuits based on CMOS at various supply voltages (0.9V, 1.2V, and 1.8V), such as positive, negative, and D-flip-flop circuits. Based on the Cadence tool, we compare the power consumption and timing behavior of these circuits to analyze the efficiency of these circuits for low-power applications.