Low-Power Approximate Multiplier Design with Optimized Delay and Area

The numerical multiplication operation serves as a fundamental computational mechanism that creates different computational approaches between digital signal processing fields and cryptography and scientific computing. Selective multipli-cation techniques play vital roles in current processor systems and embedded systems since they boost speed performance while decreasing power usage. Superior multiplication outcomes can be obtained using the Leading Zero Counters (LZCs) into Booth multipliers. A LZC system provides floating-point arrays with a check for leading zeros in binary numbers, thus enabling precise normalized calculations. The hardware system performs better when using Booth multipliers that generate few partial products to decrease system complexity and speed up calculations. Imple-mentation of the 32-bit Multiplier generates a 36.98 % reduction in Area, 15.71 % in Power consumption and 19.47% in Delay. The entire design was developed using Verilog HDL and implemented in the Xilinx Vivado environment. Additionally, synthesis was carried out using the Cadence Genus tool at 45nm technology.