A 35 ns 256 K CMOS EEPROM with error correcting circuitry

A 35-ns-access-time 256 K (32*8) EEPROM using a double-poly/double-metal n-well 1.0- mu m CMOS process, a standard two-transistor EEPROM cell, pseudodifferential sensing, and address transition detection (ATD) is described. Pseudodifferential sensing using a reference cell is used rather than the more area-intensive fully differential cell approach. In order to achieve endurance and data retention requirements at minimal die size penalty, modified Hamming codes error correcting circuitry (ECC) was implemented instead of the O-cell approach. The improvement in data retention is about two orders of magnitude over a noncorrected version. The CMOS process provides for separate optimization of high-speed read-path, as well as high-voltage write-path, devices. The high-speed devices are approximately 1.0- mu m-effective-channel-length, 23-nm gate-oxide lightly doped drain (LDD) devices, whereas the high-voltage devices are implemented in a (densely doped drain) DDD structure with about 40-nm gate-oxide thickness.<
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