3rd Crystal Oscillator in BJT Architecture Using Negative-Capacitance Circuits

This paper proposed a 3rd harmonic crystal oscillator that implemented in a BJT architecture with voltage loop tuning. The design integrated Negative Capacitance Field Effect Transistors (NCFETs) into the base circuit of the 3rd harmonic oscillator. The two ends of the negative capacitance are connected to the base and collector of the BJT element in the circuit, respectively, thereby improving noise performance and stability. The proposed design utilized TSMC's 0.18-micron process to obtain the physical chip, and validation and analysis are then performed using an SSA signal source analyzer. The phase noise is -156dBc at 1Mhz and the RMS jitter is 158.47 fsec. The result shows that the BJT architecture with NCFETs can achieve notable results in oscillator architecture.