Modular Functional Test Sequences for Test Compaction

Ensuring correct functional operation of a chip requires extensive testing. Without the constraints of maintaining functional operation conditions, structural (scan-based) tests allow high fault coverage to be achieved efficiently. To cover defects that are only exhibited under functional operation conditions, functional test sequences are used for complementing scan-based tests. One of the limitations of functional test sequences is their length, making it important to apply test compaction. To avoid losing the functional properties of a sequence when test compaction is applied at the gate level, design-for-testability (DFT) logic can be used for keeping the circuit in its functional state space. In this context, this article suggests the new concept of a modular functional test sequence consisting of subsequences that can be plugged in or out to increase the fault coverage or reduce the sequence length. To support modularity at the gate level, DFT logic is used for restoring functional states between subsequences. Modularity offers the key advantage that a single compact functional test sequence can be constructed from a given pool of functional test sequences, and the modular sequence can be updated as additional sequences become available in the pool, or additional fault models are targeted. The article develops a procedure for the generation and compaction of modular sequences using subsequences from a given pool, and presents experimental results for benchmark circuits in an academic simulation environment to demonstrate its effectiveness and limitations.