An 85 ns 16 Mb CMOS EPROM with alterable word organization

An 85-ns, 16-Mb CMOS EPROM which features alterable word organization and can be configured as either 1 M*16 b or 2 M*8 b by controlling an input signal is described. The redundancy circuit consists of an erasable PROM cell and an unerasable PROM cell for the storage of a nonfunctional address. Divided bit lines and tungsten polycide word lines are the keys to 85-ns access time. This device meets the requirements for high-density EPROMs to be used with 16-b or 32-b microprocessors. The EPROM uses 0.6- mu m n-well CMOS technology. The 2.0*1.8- mu m core cell has been scaled using (1) self-aligned trench isolation refilled with BPSG, (2) oxide-nitride-oxide (ONO) interpoly dielectrics, and (3) a bit-line contact with a silicide pad and selective chemical-vapor-deposition (CVD) tungsten. The resulting 16-Mb EPROM has a die area of 7.1*17.1 mm. Trench isolation technology minimizes the spacing between memory cells and ensures durability against the high gate voltage used in programming. Two ONO structures with a thickness equivalent to 20 nm of oxide serve as the interpoly dielectrics. To reduce the parasitic resistance of the core cell transistor, a 200-nm-thick tungsten silicide layer and a selectively deposited tungsten plug are used for the bit-line contact.<
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