Computation of 5G Communication Using FFT Based Parallel Processing Technique

As demand for effective systems increases, the optimization of hardware for operations such as the Fast Fourier Transform (FFT) is necessary, especially in environments where resources are limited. The specific method to overcome the obstacles is the use of IEEE 754 Floating Point Presentation to reduce the computation time of the mathematical operations in the Fast Fourier Transform (FFT). In this project we are going to apply the pipelined structure through which we can proceed the mathematical operations simultaneously through which we can attain a faster method of processing. The simulation of the Verilog code is done using ModelSim 6.4c tool where we obtain a hexadecimal output in the standard time of 100ms through which we get a optimized design of the Fast Fourier Transform and the physical mode of the output can be obtained by implementing in the Field Programmable Gate array (FPGA).