Total Ionizing Dose (TID) Analysis of FinFET-Based CMOS NAND and NOR Logic Gates

The total ionizing dose analysis of CMOS-based NAND and NOR logic gate is presented. In the normal operating conditions, universal logic gates function as expected. However, exposure to radiation distorts the output of both NAND and NOR gates. In particular, the NOR gate experiences significant degradation due to the parallel connection of n-FinFETs, which increases the overall trap charge density in the circuit. The accumulation of these trap charges at the gate oxide interface further deteriorates the post-radiation output, impacting the reliability of the circuit in radiation-prone environments.