Fault Simulation Algorithm for Transistor Stuck Fault in VLSI Testing

In digital integrated circuits, transistor stuck faults are major issues where transistors got either stuck short or stuck open. These faults lead to circuit malfunctions, logic errors, and power inefficiencies particularly in CMOS based digital designs. So detecting these faults is fundamental challenge in VLSI testing and Design for testability (DFT). This paper addresses the detection and simulation of transistor stuck fault. Verilog code of 2x1 multiplexer is written using switch level modelling for faulty as well as fault free design using Xilinx Vivado tool. The minimum test vectors required for stuck short and stuck open has been identified for 100% fault coverage.