Design of Low Power and High Speed CAM-assisted 9T SRAM cell on 14nm FinFET Technology

One of the key considerations in the design of low power Very-large-scale integration (VLSI) circuits is leakage power dissipation, which is entirely responsible for the circuit's overall performance. Because of the leakage and power consumption, the battery's long-lasting components lose their functionality quickly and reduce the system performance. So, in this research, the Fin-shaped Field-Effect Transistor (FinFET) based 9T SRAM cell is intended for achieving low power consumption and leakage current to speed up the write operations with the Content Addressable Memory(CAM)-assisted circuit. Moreover, the Reconfigurable Sense Amplifier (RSA) is designed to optimize the speed of memory operations, thus improving the whole performance of the SRAM circuit. In the end, a Tanner EDA tool is used to execute the proposed CAM-assisted 9T SRAM design. The performance outcomes show that the proposed design yields 10 μA leakage current, which is comparatively smaller than the existing designs.