High-Dimensional Yield Optimization for Analog Circuits via Monte Carlo Tree Search and Self-Regressive Auto-Encoder Promoted Subspace Decomposed Gaussian Process

The chase for high yield designs can effectively reduce chip manufacturing costs, making yield optimization a crucial problem in the IC community. However, the timeconsuming Monte Carlo simulations required by yield analysis hinder the traditional yield optimization methods from applying to the efficient analog circuit design flow, especially in high-dimensional design spaces. In this paper, we propose a high-dimensional yield optimization method via Monte Carlo tree search and self-regressive auto-encoder promoted subspace decomposed Gaussian process. To mitigate the common issue of over-exploration in high-dimensional optimization, a Monte Carlo tree is adopted to quickly identify promising local regions within the design space. The optimization in the selected region is realized by Bayesian optimization. To further accelerate the convergence speed of local optimization, a self-regressive autoencoder is proposed to adaptively learn for each performance metric an embedded linear subspace with dimensionality much smaller than the original design space. A specific subspace decomposed Gaussian process is constructed to model the yield variation based on the low-dimensional features of observed design parameters. A message passing algorithm is used to efficiently maximize the acquisition function, which obtains the next candidate design in intersected subspaces. Compared with the state-of-the-art methods, the proposed method achieves 2:20× – 3:99× speedup in simulation cost and 5:22×–14:33× speedup in time cost when tested in three real circuit designs.