Novel Placement of Overlay Marks to Eliminate Measurement Errors for Thick Photoresist Layers

Thick photoresists (PRs) are often used in mature tech nodes for high-dose or high-energy ion implant steps that form the deep well implants required for device isolation. The overlay control of such layers is critical in determining the channel length of the transistor. However, the PR profile of the overlay marks is prone to directional overcuts, depending on the mark’s proximity to large, exposed patterns nearby. These overcut profiles lead to erroneous overlay measurements that compromise the integrity of the feedback to Lithography’s run-to-run Advanced Process Control. This paper explores various placements of overlay marks as a solution to reduce or eliminate such overcuts and ensure maximum overlay fidelity is achieved. By placing the overlay marks at select scribe lane junctions within the reticle field, the true overlay can be measured and controlled, enabling stable electrical performance of devices.