Process Optimizations for GDDR SGRAM in Automotive Applications : Topic: DI: Defect Inspection and Reduction

An investigation into latent failures due to the formation of a resistive interface at the metal-to-via connection in automotive grade graphics SGRAM. Process improvements in via formation, increased electrical coverage targeting signal degradation, and wafer level analysis to prevent test escapes during production have been proposed. This paper aims to provide insight into the manufacturing process of graphics DRAM to target the formation of kinks near the metal-to-via connection during the wet etch clean step to prevent the formation of the resistive interface.