Correlation Between In-Situ Wafer-Level Temperature Distribution During the Etch Process and Via Resistivity

Creating vias and lines in semiconductor manufacturing demands high precision in both the lateral and depth dimensions of etched structures. When etching through the dielectric layer, it is crucial to reach the metallic contact beneath to ensure optimal electrical performance and reliability. Vias with low resistivity minimize energy loss, current dissipation, and heat generation. The cross-wafer uniformity of via resistivity is a key performance indicator for the chip manufacturing process. Identifying any non-uniformity and linking it to controllable parameters of an etch process chamber – such as electrostatic chuck temperature, exclusion ring temperature, and plasma-on properties – enables optimal tuning of the etch process and enhances yield. This is especially important during the R&D phase to ensure optimal yield in subsequent pilot line and high-volume chip manufacturing phases.In this study, we employed a wireless in-situ temperature sensor wafer to investigate the origin of a high via resistivity region within the wafer. Using production recipe conditions, we discovered a strong correlation between wafer-level temperature distribution and in-line vias resistivity results. Additionally, we used the temperature measurement wafer to assess the impact of electrostatic chuck temperature, edge ring temperature, and plasma-on properties on wafer-level temperature. These findings offer valuable insights into the performance of the dielectric plasma etch processes and equipment, enabling process development, optimization, chamber matching and improved high-volume manufacturing process monitoring.