Design and Comparative Analysis of Half and Full Adders Using CMOS and Pass Transistor Logic Styles

Energy-efficient designs are becoming more and more necessary as digital systems develop, particularly in applications with limited power, such as embedded and mobile systems. CMOS circuits still experience power losses during switching transitions, despite their widespread use due to their efficiency. To maximize energy usage, alternative logic designs including CMOS NAND gates, CMOS transmission gates, and NMOS pass transistor logic are investigated. The primary objective of this project is to design and test low-power, space-efficient half-adder and full-adder circuits using these three logic types. The designs are implemented and simulated to analyze key performance specifications namely transistor count, propagation latency, and utilization of power. The comparative analysis offers a means to optimize digital circuits for practical low-power applications by shedding light on how various logic types might be used in contemporary VLSI design.