Performance Analysis of 4-Bit Hybrid Low Power Carry Select Adder using FinFET Technology

Adder is a fundamental component of any digital processor, facilitating core computations including arithmetic operations and various transforms. However, conventional adder circuits such as the ripple carry adder not only introduce a delay but also increase the power. Optimizing the circuit's power is essential for the efficient operation of the adder. The carry select adder (CSA) is one of the high-speed adders used in digital circuits. Conventional CSAs encounter limitations in power efficiency and area, which can pose challenges in lowpower applications. Therefore, low-power CSA architectures need to be designed. The proposed four CSA architectures introduce hybrid adder designs combining pass transistor logic (PTL) and gate diffusion input (GDI) techniques for improved power and area efficiency. Proposed-1 and proposed-2 incorporate GDI and PTL-based XOR gates along with CMOS AND logic, achieving power reductions of 21.57% and 21.63%, respectively. In contrast, proposed-3 and proposed-4 implement GDI and PTL-based XOR with PTL AND logic, resulting in even higher power savings of 46.28% and 46.82% compared to reference CSA. Cadence Virtuoso is used for circuit design using 18nm FinFET technology, and simulations were conducted using Spectre.