RTL Design of an Accelerator for Softmax Layer in Deep Neural Networks

Softmax serves as the final classification layer in deep neural networks. As the speed of other layers in deep neural networks continues to improve, there is a growing need for f lexible and efficient designs for the Softmax layer. In this paper, we propose and design an accelerator for the Softmax layer. The accelerator is designed at the RTL (Register Transfer Level) using Verilog HDL (Hardware Description Language). In this design, we use a 32-bit single precision floating point and convert it to 16-bit to reduce the hardware resources. Additionally, the design incorporates the AXI4-Stream interface, enabling it to handle inputs of any size. We simulated and implemented the design on the Xilinx FPGA platform to evaluate its superiority. Experimental results show that the accelerator achieves high accuracy, with an average error of 1.92E-04 compared to the software version. Simultaneously, it ran 9.55× faster than the software implementations on a personal computer.