Hardware Efficient Realization of 128 bit Advanced Encryption Standard in FPGA

In the current digital world, data security is a top concern. With the aid of current standards, text and image data are typically well safeguarded. However, voice communications security remains a difficult challenge. The issue of data security is becoming more pressing as technology continues to progress. The hackers may breach any security system since they have access to cutting-edge new tools and methods. As a result, concerns over data security are growing. Either software or hardware implementations are used to secure data. Because Field Programmable Gate Arrays (FPGA) are more efficient, flexible, and less complex than other hardware implementation methods, they are used in this paper. The Advanced Encryption Standard (AES) algorithm, one of the security methods, is the main subject of this work's hardware implementation. This encryption technique is adaptable and is employed in military settings. The original 128-bit plain text can be recovered using the same key for decryption. The non-LUT based implementation of AES S-box and inverse S-box is the preferable method for high-speed applications. The Quartus-II 9.1 program software is used to run the AES algorithm. In this paper AES algorithm's design implementation and the resources used to implement it on FPGA are covered.