Optimization of IDlin–IDsat Mismatch in 1200 V P-Channel LDMOS by Channel-End Potential Modulation

The current mismatch between the linear region ( ${I}_{\text {Dlin}}\text {)}$ and saturation region ( ${I}_{\text {Dsat}}\text {)}$ of the 1200 V P-channel lateral diffused MOS (PLDMOS) hinders the design of the level shift circuit, because the value of the load resistor is difficult to determine. In this work, high P-drift doping concentration and partially spaced gate (PSG) are used for channel-end potential modulation, and the global potential control technology is adopted to maintain high breakdown voltage (BV). By increasing channel-end potential, the saturation of intrinsic MOS (IMOS) is promoted to ensure the PLDMOS operating in the saturation region, and then the excessive ${I}_{\text {Dsat}}$ is limited. Besides, the high P-drift doping concentration also enhances the ${I}_{\text {Dlin}}$ of PLDMOS. The experimental results show that the ratio of ${I}_{\text {Dlin}}$ (at ${V}_{\text {GS}} = -15$ V and ${V}_{\text {DS}} = -5$ V) to ${I}_{\text {Dsat}}$ (at ${V}_{\text {GS}} = -15$ V and ${V}_{\text {DS}} = -1200$ V) has been increased from 3.9% to 36.4%. The off-state BV and on-state BV at ${V}_{\text {GS}} = -15$ V of the proposed PLDMOS are 1681 and 1587 V, respectively.