Tutorial: Calibration Techniques in PLLs

Digitally assisted PLLs have become the mainstream solution to design lower jitter and more agile clock generators in modern CMOS processes. In this tutorial, after introducing the basics of adaptive filtering, we describe some of the calibration techniques for low-jitter fast-switching frequency synthesizers. These include techniques to correct for digital-time-converter (DTC) gain errors and nonlinearity, to calibrate loop bandwidth, and to speed up lock transients. The tutorial will discuss the issues in the practical implementation of the different approaches and present some state-of-the-art examples.