Modeling of 6T-SRAM Transistor Failure and Faults Caused by Injected Noise in Neural Networkst

By conducting failure simulations on the classic 6T-SRAM model across different transistor process nodes, the bit-flip behavior during read and write operations under failure conditions was observed. Based on the simulation results, a probabilistic model for the failure scenarios was established. This failure model was then applied to various neural networks by injecting different levels of noise. It was observed that the noise intensity exhibited a locally negative correlation with the prediction accuracy of the neural networks.