Tutorial: Fundamentals of Ultra-Low Voltage Embedded Memory Design

To meet the energy efficiency demands of future applications, system-on-chip (SoC) designs continue to march towards ultra-low-voltage operation. This tutorial will address the fundamental challenges for embedded memory operation at low voltages in advanced process technologies, and cover single and multi-port SRAM, logic flip-flop, logic latch arrays, and eFuse technologies, prevalent in embedded design use. Memory assist circuits, repair, error correction, multi-VCC array design, clocking and min-delay design strategies relevant to enabling ultra-low and near-threshold system operation will be explored. System designers will walk away with a stronger understanding of how to better navigate embedded memory usage in ultra-low-voltage designs.