Tutorial: All-Digital PLLs: From Fundamental Concepts to Future Trends

Frequency synthesis has become ubiquitous in chip designs for clocking, RF, and data sampling. Traditional analog PLLs have moved to digital implementations, for area, power, and technology portability. This tutorial describes the evolution of all-digital PLLs, from the basic digitization of oscillator control at integer ratios, to low-noise flexible fractional-N frequency synthesis with digital-to-time converters (DTCs). The evolution of two noise-critical blocks is described: time-to-digital converters (TDCs) and fractional dividers. This includes voltage-based TDCs, such as time amplifiers and successive-approximation-register (SAR) architectures, and various DTCs for fractional-divider noise reduction. It concludes with architectures at the limits of noise and size, namely bang-bang TDCs, and looks at future digital PLL trends. The presentation emphasizes key considerations for digital systems, including fast dynamic frequency scaling (DFS), fine resolution, and noise mitigation.