Tutorial: Signal Integrity Analysis for Gbs Links

Signal integrity analysis permits circuit designers to model and evaluate high-speed I/O with fast simulations, both for quick evaluation of design alternatives and accurate high-level verification. This tutorial covers theoretical underpinnings and practical tools for behavioral modeling and simulation of wireline chip-to-chip links. Attendees will learn to accurately model lossy interconnects, packaging parasitics, and transceiver front-ends. The tutorial will also introduce nondeterministic impairments such as noise and jitter, and the modeling of linear and decision-feedback equalization. Analysis techniques amenable to both circuit-level (netlist) simulators and high-level modeling (e.g. Matlab) tools will be covered.