Tutorial: Clock and Data Recovery Architectures and Circuits

This tutorial provides ground theory and practical strategies for the design of clock-and-data-recovery circuits. We begin by relating performance metrics such as jitter transfer, jitter tolerance, and jitter peaking to CDR loop components and use these relationships to elucidate application-specific design challenges and tradeoffs. Following this, we will discuss both architectural- and circuit-level techniques to manage/overcome these tradeoffs. Specifically, we would compare different architectures: bang-bang vs. linear, digital vs. analog vs. hybrid loops, oscillator vs. phase interpolator, and reference-less vs. reference-based CDRs.