A Systematic Design Method Based on Vector Analysis for mmW DCML Divider

The traditional RC delay model and the small-signal model do not suffice for a precise analysis of the dynamic current mode logic (DCML) divider in the millimeter-wave (mmW) frequency band. This paper explores the current vector model and examines the prerequisites for the proper functioning of the DCML, including phase, gain, and amplitude aspects, using expressions and vector diagrams as references. To fulfill the frequency division requirements of mmW ultra-wideband phaselocked loops, a broadband DCML4 divider has been designed based on the aforementioned analysis. Simulation results show that with an input power of -4 dBm, the maximum frequency division range for a single sub-band can reach up to 137.5% (from 5 to 27 GHz). The center frequency is adjusted via biasing, enabling the total frequency coverage to achieve 150% (ranging from 5 to 35 GHz). At a supply voltage of 1.2 V, the average power consumption is only 6.72 mW.