Advancements in IC Substrate Packaging: A Process to Metallize Embedded Trench for Enhanced Performance and Sustainability

As we navigate the evolving landscape of electronics miniaturization, the role of high-yield, cost-effective integrated circuit (IC) substrates becomes increasingly pivotal. These substrates are essential for facilitating dense interconnections between chips and boards. Central to optimizing the use of substrate space is the reduction of the distance between copper (Cu) traces, also referred to as line and space (L/S). Whereas traditional PCB technology typically features L/S dimensions greater than 40 µm, cutting-edge wafer-level technologies have achieved L/S ratios as fine as 2 µm, Over the last ten years, the dimensions of chips and their associated L/S on substrates have significantly contracted. This trend towards smaller chip sizes and reduced L/S distances presents unique challenges to both the PCB and semiconductor industries. Fan-out panel-level packaging (FOPLP) represents a burgeoning technology that aims to merge the realms of PCB and IC/semiconductor manufacturing more closely. Although still in its nascent stages, the potential for high-volume production in this sector offers substantial economic incentives for pioneering innovative solutions that facilitate technology adoption. A critical quality metric in this area is the uniformity of plating, or planarity, which ensures the flatness of trace and via tops—key in multilayer processes where deviations in lower layers can propagate upwards, potentially leading to severe failures like short circuits. Moreover, a non-planar surface can degrade signal transmission, emphasizing the need for plating solutions that achieve consistent, planar results without necessitating additional post-treatment steps. We introduce a cutting-edge process for embedded trench substrate (ETS) that ensures remarkably uniform plating and precision in right-angle patterns, crucial for high-speed data transfers and enhanced device reliability. Our process achieves a significant uniformity with less than 1 µm variation across components, enhancing yield and component integrity. By delivering a coplanar surface and robust square trace profiles, this method eliminates the need for subsequent polishing steps, streamlining production and improving the durability of the final products.